
module OH_TSOH(
   RESET,
   TCLK_155M,

   MPI_TXJ0_DATA,
   MPI_TXJ0_MODE,
   MPI_TXK1K2,              // K1/K2 byte data, BIT15-BIT8 are K1 byte, BIT7-BIT0 are K2 byte
   MPI_TXS1,
   MPI_TX_SOH_LOOP_EN,
   RSOH_B2_CNT,
   
   DBIN_TDATA,
   DBIN_FCNT8,
   DBIN_FCNT270,
   DBIN_FCNT9,
   DBIN_MFCNT64,

   TSOH_TDATA,
   TSOH_FCNT8,
   TSOH_FCNT270,
   TSOH_FCNT9,
  // data bus from receive side, used for SOH loop
   RX_RCLK155M,
   RX_DBIN_FAS_FAIL,
   RX_DBIN_FCNT8,
   RX_DBIN_FCNT270,
   RX_DBIN_FCNT9,
   RX_DBIN_DATA
   );

input              RESET;
input              TCLK_155M;

input[127:0]       MPI_TXJ0_DATA;
input              MPI_TXJ0_MODE;
input[15:0]        MPI_TXK1K2;
input[7:0]         MPI_TXS1;
input              MPI_TX_SOH_LOOP_EN;
input[15:0]        RSOH_B2_CNT;
   
input[63:0]        DBIN_TDATA;
input[2:0]         DBIN_FCNT8;
input[8:0]         DBIN_FCNT270;
input[3:0]         DBIN_FCNT9;
input[5:0]         DBIN_MFCNT64;

output reg[63:0]   TSOH_TDATA;
output reg[2:0]    TSOH_FCNT8;
output reg[8:0]    TSOH_FCNT270;
output reg[3:0]    TSOH_FCNT9;

input              RX_RCLK155M;
input              RX_DBIN_FAS_FAIL;
input[2:0]         RX_DBIN_FCNT8;
input[8:0]         RX_DBIN_FCNT270;
input[3:0]         RX_DBIN_FCNT9;
input[63:0]        RX_DBIN_DATA;

// 

// capture input MPI signals TCLK_155M, convert received RSOH_B2_CNT to TCLK_155M
reg[127:0]         TSOH_TXJ0_DATA;
reg                TSOH_TXJ0_MODE;
reg[15:0]          TSOH_TXK1K2;
reg[7:0]           TSOH_TXS1;
reg[15:0]          TSOH_REI_CNT;
reg                TSOH_TX_SOH_LOOP_EN;
reg[7:0]           SINS_TSOH_J0;

// signals after SOH bytes loop control
wire[63:0]         SOH_LOOP_TDATA;
wire[2:0]          SOH_LOOP_FCNT8;
wire[8:0]          SOH_LOOP_FCNT270;
wire[3:0]          SOH_LOOP_FCNT9;
wire[5:0]          SOH_LOOP_MFCNT64;

// delay all input 1 clock cycle wait for SOH bytes select
reg[63:0]          SINS_TDATA;
reg[2:0]           SINS_FCNT8;
reg[8:0]           SINS_FCNT270;
reg[3:0]           SINS_FCNT9;

// delay signals wait for B2 RAMs read latency
reg[63:0]          TXB2_M1_TDATA, TXB2_M2_TDATA;
reg[2:0]           TXB2_M1_FCNT8, TXB2_M2_FCNT8;
reg[8:0]           TXB2_M1_FCNT270, TXB2_M2_FCNT270;
reg[3:0]           TXB2_M1_FCNT9, TXB2_M2_FCNT9;

reg[4:0]           TXB2_READ_CHNN, TXB2_WRITE_CHNN;
reg                TXB2_B2CAL_EN;
reg                TXB2_B2CAL_START;
reg                TXB2_B2BYTE_EN;
reg[63:0]          TXB2_WR_B2CALC;                          // read/write B2 calculating value
wire[63:0]         TXB2_RO_B2CALC;
wire[63:0]         TXB2_RO_B2RESULT;                        // saved B2 value of previous frame

wire               B2CALC_RAM_CLKA, B2CALC_RAM_CLKB;        // sginals for B2 calculate RAM
wire               B2CALC_RAM_WEA;
wire[5:0]          B2CALC_RAM_ADDRA, B2CALC_RAM_ADDRB;
wire[63:0]         B2CALC_RAM_DINA, B2CALC_RAM_DOUTB;

wire               B2RESULT_RAM_CLKA, B2RESULT_RAM_CLKB;    // sginals for B2 result RAM, the RAM save the B2 result of previous frame
wire               B2RESULT_RAM_WEA;
wire[5:0]          B2RESULT_RAM_ADDRA, B2RESULT_RAM_ADDRB;
wire[63:0]         B2RESULT_RAM_DINA, B2RESULT_RAM_DOUTB;





OH_SOH_LOOP           INST_OH_SOH_LOOP(
   .GLB_RESET         ( RESET ),
  // receive data bus
   .RCLK_155M         ( RX_RCLK155M ),
   .FRM2OH_FAS_FAIL   ( RX_DBIN_FAS_FAIL ),
   .FRM2OH_FCNT8      ( RX_DBIN_FCNT8[2:0] ),
   .FRM2OH_FCNT270    ( RX_DBIN_FCNT270[8:0] ),
   .FRM2OH_FCNT9      ( RX_DBIN_FCNT9[3:0] ),
   .FRM2OH_DATA       ( RX_DBIN_DATA[63:0] ),
  // transmit data bus from loop control
   .TX_CLK155M        ( TCLK_155M ),
   .TX_SOH_LOOP_EN    ( TSOH_TX_SOH_LOOP_EN ),
   .TX_DBIN_TDATA     ( DBIN_TDATA[63:0] ),
   .TX_DBIN_FCNT8     ( DBIN_FCNT8[2:0] ),
   .TX_DBIN_FCNT270   ( DBIN_FCNT270[8:0] ),
   .TX_DBIN_FCNT9     ( DBIN_FCNT9[3:0] ),
   .TX_DBIN_MFCNT64   ( DBIN_MFCNT64[5:0] ),
  // transmit data bus to SOH insert
   .TX_DBOUT_TDATA    ( SOH_LOOP_TDATA[63:0] ),
   .TX_DBOUT_FCNT8    ( SOH_LOOP_FCNT8[2:0] ),
   .TX_DBOUT_FCNT270  ( SOH_LOOP_FCNT270[8:0] ),
   .TX_DBOUT_FCNT9    ( SOH_LOOP_FCNT9[3:0] ),
   .TX_DBOUT_MFCNT64  ( SOH_LOOP_MFCNT64[5:0] )
   );


//****** Section 0: convert MPI signals and RSOH_B2_CNT to TCLK_155M clock domain ******//
always @(posedge RESET or posedge TCLK_155M) begin
   if ( RESET==1'b1 ) begin
      TSOH_TXJ0_DATA[127:0]                  <= 128'd0;
      TSOH_TXJ0_MODE                         <= 1'b0;
      TSOH_TXK1K2[15:0]                      <= 16'd0;
      TSOH_TXS1[7:0]                         <= 8'd0;
      TSOH_TX_SOH_LOOP_EN                    <= 1'b0;
      TSOH_REI_CNT[15:0]                     <= 16'd0;
   end
   else begin
      TSOH_TXJ0_DATA[127:0]                  <= MPI_TXJ0_DATA[127:0];
      TSOH_TXJ0_MODE                         <= MPI_TXJ0_MODE;
      TSOH_TXK1K2[15:0]                      <= MPI_TXK1K2[15:0];
      TSOH_TXS1[7:0]                         <= MPI_TXS1[7:0];
      TSOH_TX_SOH_LOOP_EN                    <= MPI_TX_SOH_LOOP_EN;
      TSOH_REI_CNT[15:0]                     <= RSOH_B2_CNT[15:0];
   end
end

always @( SOH_LOOP_MFCNT64 or TSOH_TXJ0_DATA or TSOH_TXJ0_MODE) begin
   if ( TSOH_TXJ0_MODE==1'b1 ) begin
      case ( SOH_LOOP_MFCNT64[3:0] )
      4'h0:     SINS_TSOH_J0[7:0]   <= TSOH_TXJ0_DATA[8*0+7:8*0];
      4'h1:     SINS_TSOH_J0[7:0]   <= TSOH_TXJ0_DATA[8*1+7:8*1];
      4'h2:     SINS_TSOH_J0[7:0]   <= TSOH_TXJ0_DATA[8*2+7:8*2];
      4'h3:     SINS_TSOH_J0[7:0]   <= TSOH_TXJ0_DATA[8*3+7:8*3];
      4'h4:     SINS_TSOH_J0[7:0]   <= TSOH_TXJ0_DATA[8*4+7:8*4];
      4'h5:     SINS_TSOH_J0[7:0]   <= TSOH_TXJ0_DATA[8*5+7:8*5];
      4'h6:     SINS_TSOH_J0[7:0]   <= TSOH_TXJ0_DATA[8*6+7:8*6];
      4'h7:     SINS_TSOH_J0[7:0]   <= TSOH_TXJ0_DATA[8*7+7:8*7];
      4'h8:     SINS_TSOH_J0[7:0]   <= TSOH_TXJ0_DATA[8*8+7:8*8];
      4'h9:     SINS_TSOH_J0[7:0]   <= TSOH_TXJ0_DATA[8*9+7:8*9];
      4'hA:     SINS_TSOH_J0[7:0]   <= TSOH_TXJ0_DATA[8*10+7:8*10];
      4'hB:     SINS_TSOH_J0[7:0]   <= TSOH_TXJ0_DATA[8*11+7:8*11];
      4'hC:     SINS_TSOH_J0[7:0]   <= TSOH_TXJ0_DATA[8*12+7:8*12];
      4'hD:     SINS_TSOH_J0[7:0]   <= TSOH_TXJ0_DATA[8*13+7:8*13];
      4'hE:     SINS_TSOH_J0[7:0]   <= TSOH_TXJ0_DATA[8*14+7:8*14];
      4'hF:     SINS_TSOH_J0[7:0]   <= TSOH_TXJ0_DATA[8*15+7:8*15];
      default:  SINS_TSOH_J0[7:0]   <= 8'h00;
      endcase
   end
   else begin
                SINS_TSOH_J0[7:0]   <= TSOH_TXJ0_DATA[8*0+7:8*0];
   end
end

always @(posedge RESET or posedge TCLK_155M) begin
   if ( RESET==1'b1 )
      SINS_TDATA[63:0]                        <= 64'd0;
   else begin
      if ( SOH_LOOP_FCNT9[3:0]==4'd0 && ( SOH_LOOP_FCNT270[8:0]==9'd0 || SOH_LOOP_FCNT270[8:0]==9'd1 || SOH_LOOP_FCNT270[8:0]==9'd2) ) begin      // A1
         SINS_TDATA[63:0]                     <= 64'hF6F6F6F6_F6F6F6F6;
      end
      else if ( SOH_LOOP_FCNT9[3:0]==4'd0 && ( SOH_LOOP_FCNT270[8:0]==9'd3 || SOH_LOOP_FCNT270[8:0]==9'd4 || SOH_LOOP_FCNT270[8:0]==9'd5)) begin  // A2
         SINS_TDATA[63:0]                     <= 64'h28282828_28282828;
      end
//    else if ( SOH_LOOP_FCNT9[3:0]==4'd3 &&  SOH_LOOP_FCNT270[8:0]<9'h09) begin                                                                 // AU Point
//       if ( SOH_LOOP_FCNT270[8:0]==9'd0 && SOH_LOOP_FCNT8[2:0]==3'd0 )                                                                         // first H1
//          SINS_TDATA[63:0]                  <= 64'h6A9B9B9B_9B9B9B9B;
//       else if ( SOH_LOOP_FCNT270[8:0]==9'd1 || SOH_LOOP_FCNT270[8:0]==9'd2 || ( SOH_LOOP_FCNT270[8:0]==9'd0 && SOH_LOOP_FCNT8[2:0]!=3'd0 ) )  // others H1
//          SINS_TDATA[63:0]                  <= 64'h9B9B9B9B_9B9B9B9B;
//       else if ( SOH_LOOP_FCNT270[8:0]==9'd3 && SOH_LOOP_FCNT8[2:0]==3'd0 )                                                                    // first H2
//          SINS_TDATA[63:0]                  <= 64'h0AFFFFFF_FFFFFFFF;
//       else if ( SOH_LOOP_FCNT270[8:0]==9'd4 || SOH_LOOP_FCNT270[8:0]==9'd5 || ( SOH_LOOP_FCNT270[8:0]==9'd3 && SOH_LOOP_FCNT8[2:0]!=3'd0 ) )  // others H2
//          SINS_TDATA[63:0]                 <= 64'hFFFFFFFF_FFFFFFFF;
//       else
//          SINS_TDATA[63:0]                 <= 64'd0;                                                                                           // H3
//    end
      else if ( TSOH_TX_SOH_LOOP_EN==1'b0 ) begin                                                                                                // select bytes that can be loop back
         if ( SOH_LOOP_FCNT9[3:0]==4'd0 && (SOH_LOOP_FCNT270[8:0]==9'd6 || SOH_LOOP_FCNT270[8:0]==9'd7 || SOH_LOOP_FCNT270[8:0]==9'd8)) begin
            if ( SOH_LOOP_FCNT9[3:0]==4'd0 && SOH_LOOP_FCNT270[8:0]==9'd6 && SOH_LOOP_FCNT8[2:0]==3'd0 )                                         // J0
               SINS_TDATA[63:0]              <= {SINS_TSOH_J0[7:0], 56'h555555_55555555};
            else
               SINS_TDATA[63:0]              <= 64'h50515253_54555657;                                                                           // un-scramble bits afters J0
         end
         else if ( SOH_LOOP_FCNT9[3:0]==4'd4 && SOH_LOOP_FCNT270[8:0]==9'd3 && SOH_LOOP_FCNT8[2:0]!=3'd0 ) begin                                 // K1 byte, Row 4
               SINS_TDATA[63:0]              <= { TSOH_TXK1K2[15:8], 56'h000000_00000000 };
         end
         else if ( SOH_LOOP_FCNT9[3:0]==4'd4 && SOH_LOOP_FCNT270[8:0]==9'd6 && SOH_LOOP_FCNT8[2:0]!=3'd0 ) begin                                 // K2 byte, Row 4
               SINS_TDATA[63:0]              <= { TSOH_TXK1K2[7:0], 56'h000000_00000000 };
         end
         else if ( SOH_LOOP_FCNT9[3:0]==4'd8 && SOH_LOOP_FCNT270[8:0]==9'd3 && SOH_LOOP_FCNT8[2:0]!=3'd0) begin                                  // M0 M1
               SINS_TDATA[63:0]              <= {8'd0, TSOH_REI_CNT[15:0], 40'd0};
         end
         else if ( SOH_LOOP_FCNT9[3:0]==4'd8 && SOH_LOOP_FCNT270[8:0]==9'd0 && SOH_LOOP_FCNT8[2:0]!=3'd0) begin                                  // S1 byte, Row 8
               SINS_TDATA[63:0]              <= { TSOH_TXS1[7:0], 56'h000000_00000000 };
         end
         else begin
               SINS_TDATA[63:0]              <= SOH_LOOP_TDATA[63:0];
         end
      end
      else begin
         if ( SOH_LOOP_FCNT9[3:0]==4'd0 && (SOH_LOOP_FCNT270[8:0]==9'd6 || SOH_LOOP_FCNT270[8:0]==9'd7 || SOH_LOOP_FCNT270[8:0]==9'd8)) begin
            if ( SOH_LOOP_FCNT9[3:0]==4'd0 && SOH_LOOP_FCNT270[8:0]==9'd6 && SOH_LOOP_FCNT8[2:0]==3'd0 )                                         // J0
               SINS_TDATA[63:0]              <= {SOH_LOOP_TDATA[63:56], 56'h555555_55555555};
            else
               SINS_TDATA[63:0]              <= 64'h50515253_54555657;                                                                           // un-scramble bits afters J0
         end
         else begin
            SINS_TDATA[63:0]                 <= SOH_LOOP_TDATA[63:0];
         end
      end
   end
end

always @(posedge RESET or posedge TCLK_155M) begin
   if ( RESET==1'b1 ) begin
      SINS_FCNT8[2:0]                        <= 3'd0;
      SINS_FCNT270[8:0]                      <= 9'd0;
      SINS_FCNT9[3:0]                        <= 4'd0;
   end
   else begin
      SINS_FCNT8[2:0]                        <= SOH_LOOP_FCNT8[2:0];
      SINS_FCNT270[8:0]                      <= SOH_LOOP_FCNT270[8:0];
      SINS_FCNT9[3:0]                        <= SOH_LOOP_FCNT9[3:0];
   end
end





//******       Section 2: B2 calculate      ******//
always @(posedge RESET or posedge TCLK_155M) begin
   if ( RESET==1'b1 ) begin
      TXB2_M1_TDATA[63:0]            <= 64'd0;
      TXB2_M2_TDATA[63:0]            <= 64'd0;
      TXB2_M1_FCNT8[2:0]             <= 3'd0;
      TXB2_M2_FCNT8[2:0]             <= 3'd0;
      TXB2_M1_FCNT270[8:0]           <= 9'd0;
      TXB2_M2_FCNT270[8:0]           <= 9'd0;
      TXB2_M1_FCNT9[3:0]             <= 4'd0;
      TXB2_M2_FCNT9[3:0]             <= 4'd0;
   end
   else begin
      TXB2_M1_TDATA[63:0]            <= SINS_TDATA[63:0];
      TXB2_M2_TDATA[63:0]            <= TXB2_M1_TDATA[63:0];
      TXB2_M1_FCNT8[2:0]             <= SINS_FCNT8[2:0];
      TXB2_M2_FCNT8[2:0]             <= TXB2_M1_FCNT8[2:0];
      TXB2_M1_FCNT270[8:0]           <= SINS_FCNT270[8:0];
      TXB2_M2_FCNT270[8:0]           <= TXB2_M1_FCNT270[8:0];
      TXB2_M1_FCNT9[3:0]             <= SINS_FCNT9[3:0] ;
      TXB2_M2_FCNT9[3:0]             <= TXB2_M1_FCNT9[3:0];
   end
end

// generate read/write address, read address generated from SINS_* counts, write address generated from TXB2_M2_* counts because of RAM read lactency
always @(posedge RESET or posedge TCLK_155M) begin
   if ( RESET==1'b1 )
      TXB2_READ_CHNN[4:0]                  <= 5'd0;
   else begin
      if ( SINS_FCNT9[3:0]==4'd8 && SINS_FCNT270[8:0]==9'd269 && SINS_FCNT8[2:0]==3'd7 )
         TXB2_READ_CHNN[4:0]               <= 5'd0;
      else if ( TXB2_READ_CHNN[4:0]==5'd23 )
         TXB2_READ_CHNN[4:0]               <= 5'd0;
      else
         TXB2_READ_CHNN[4:0]               <= TXB2_READ_CHNN[4:0] +5'd1;
   end
end
always @(posedge RESET or posedge TCLK_155M) begin
   if ( RESET==1'b1 )
      TXB2_WRITE_CHNN[4:0]                 <= 5'd0;
   else begin
      if ( TXB2_M2_FCNT9[3:0]==4'd8 && TXB2_M2_FCNT270[8:0]==9'd269 && TXB2_M2_FCNT8[2:0]==3'd7 )
         TXB2_WRITE_CHNN[4:0]              <= 5'd0;
      else if ( TXB2_WRITE_CHNN[4:0]==5'd23 )
         TXB2_WRITE_CHNN[4:0]              <= 5'd0;
      else
         TXB2_WRITE_CHNN[4:0]              <= TXB2_WRITE_CHNN[4:0] +5'd1;
   end
end

// generate B2 calculate restart,enable; B2 byte position. Generated from TXB2_M2_*
always @( TXB2_M2_FCNT270 or TXB2_M2_FCNT9 ) begin
   if ( TXB2_M2_FCNT9[3:0]==4'd0 && TXB2_M2_FCNT270[8:0]<9'd9 )
      TXB2_B2CAL_EN                        <= 1'b0;
   else if ( TXB2_M2_FCNT9[3:0]==4'd1 && TXB2_M2_FCNT270[8:0]<9'd9 )
      TXB2_B2CAL_EN                        <= 1'b0;
   else if ( TXB2_M2_FCNT9[3:0]==4'd2 && TXB2_M2_FCNT270[8:0]<9'd9 )
      TXB2_B2CAL_EN                        <= 1'b0;
   else
      TXB2_B2CAL_EN                        <= 1'b1;
end
always @( TXB2_M2_FCNT270 or TXB2_M2_FCNT9 ) begin
   if ( TXB2_M2_FCNT9[3:0]==4'b0 && (TXB2_M2_FCNT270[8:0]==9'd9 || TXB2_M2_FCNT270[8:0]==9'd10 || TXB2_M2_FCNT270[8:0]==9'd11) )
      TXB2_B2CAL_START                     <= 1'b1;
   else
      TXB2_B2CAL_START                     <= 1'b0;
end
always @( TXB2_M2_FCNT270 or TXB2_M2_FCNT9 ) begin
   if ( TXB2_M2_FCNT9[3:0]==4'd4 && (TXB2_M2_FCNT270[8:0]==9'd0 || TXB2_M2_FCNT270[8:0]==9'd1 || TXB2_M2_FCNT270[8:0]==9'd2) )
      TXB2_B2BYTE_EN                       <= 1'b1;
   else
      TXB2_B2BYTE_EN                       <= 1'b0;
end



// calculate B2 for every frame
always @( TXB2_B2CAL_START or TXB2_B2CAL_EN or TXB2_M2_TDATA or TXB2_RO_B2CALC or TXB2_B2BYTE_EN or TXB2_RO_B2RESULT) begin
   if ( TXB2_B2CAL_EN==1'b1 )  begin
      if ( TXB2_B2CAL_START==1'b1 )
         TXB2_WR_B2CALC[63:0]             <= TXB2_M2_TDATA[63:0];
      else begin
         if ( TXB2_B2BYTE_EN==1'b1 )      // replace data with B2 of previous frame
            TXB2_WR_B2CALC[63:0]         <= TXB2_RO_B2RESULT[63:0] ^ TXB2_RO_B2CALC[63:0];
         else
            TXB2_WR_B2CALC[63:0]         <= TXB2_M2_TDATA[63:0] ^ TXB2_RO_B2CALC[63:0];
      end
   end
   else begin
         TXB2_WR_B2CALC[63:0]             <= TXB2_RO_B2CALC[63:0];
   end
end


  assign  B2CALC_RAM_CLKA = TCLK_155M;
  assign  B2CALC_RAM_CLKB = TCLK_155M;
  assign  B2CALC_RAM_WEA  = TXB2_B2CAL_EN;
  assign  B2CALC_RAM_ADDRA[5:0]  = { 1'b0, TXB2_WRITE_CHNN[4:0] };
  assign  B2CALC_RAM_ADDRB[5:0]  = { 1'b0, TXB2_READ_CHNN[4:0] };
  assign  B2CALC_RAM_DINA[63:0]  = TXB2_WR_B2CALC[63:0];
  assign  TXB2_RO_B2CALC[63:0]   = B2CALC_RAM_DOUTB[63:0];
 
OH_TSOH_B2RAM_WRAP           INST_B2RAM_CAL(
    .CLKA                    ( B2CALC_RAM_CLKA ),
    .WEA                     ( B2CALC_RAM_WEA ),
    .ADDRA                   ( B2CALC_RAM_ADDRA[5:0] ),
    .DINA                    ( B2CALC_RAM_DINA[63:0] ),
    .CLKB                    ( B2CALC_RAM_CLKB ),
    .ADDRB                   ( B2CALC_RAM_ADDRB[5:0] ),
    .DOUTB                   ( B2CALC_RAM_DOUTB[63:0] )
   );

// capture all B2 result into B2RAM_RESULT at the end of frame
  assign  B2RESULT_RAM_CLKA  = TCLK_155M;
  assign  B2RESULT_RAM_CLKB  = TCLK_155M;
  assign  B2RESULT_RAM_WEA   = ( TXB2_M2_FCNT9[3:0]==4'd8 && (TXB2_M2_FCNT270[8:0]==9'd267 || TXB2_M2_FCNT270[8:0]==9'd268 || TXB2_M2_FCNT270[8:0]==9'd269) );
  assign  B2RESULT_RAM_ADDRA[5:0]  = { 1'b0, TXB2_WRITE_CHNN[4:0] };
  assign  B2RESULT_RAM_ADDRB[5:0]  = { 1'b0, TXB2_READ_CHNN[4:0] };
  assign  B2RESULT_RAM_DINA[63:0]  = TXB2_WR_B2CALC[63:0];  // same as B2 calculate result
  assign  TXB2_RO_B2RESULT[63:0]   = B2RESULT_RAM_DOUTB[63:0];

OH_TSOH_B2RAM_WRAP           INST_B2RAM_RESULT(
    .CLKA                    ( B2RESULT_RAM_CLKA ),
    .WEA                     ( B2RESULT_RAM_WEA ),
    .ADDRA                   ( B2RESULT_RAM_ADDRA[5:0] ),
    .DINA                    ( B2RESULT_RAM_DINA[63:0] ),
    .CLKB                    ( B2RESULT_RAM_CLKB ),
    .ADDRB                   ( B2RESULT_RAM_ADDRB[5:0] ),
    .DOUTB                   ( B2RESULT_RAM_DOUTB[63:0] )
   );





//****** B2 instert into data stream ******//
always @(posedge RESET or posedge TCLK_155M) begin
   if ( RESET==1'b1 ) begin
      TSOH_TDATA[63:0]                    <= 64'd0;
      TSOH_FCNT8[2:0]                     <= 3'd0;
      TSOH_FCNT270[8:0]                   <= 9'd0;
      TSOH_FCNT9[3:0]                     <= 4'd0;
   end
   else begin
      TSOH_FCNT8[2:0]                     <= TXB2_M2_FCNT8[2:0];
      TSOH_FCNT270[8:0]                   <= TXB2_M2_FCNT270[8:0];
      TSOH_FCNT9[3:0]                     <= TXB2_M2_FCNT9[3:0];
      if ( TXB2_B2BYTE_EN==1'b1 )
         TSOH_TDATA[63:0]                 <= TXB2_RO_B2RESULT[63:0];
      else
         TSOH_TDATA[63:0]                 <= TXB2_M2_TDATA[63:0];
   end
end

endmodule